dr_proc.h File Reference

Utility routines for identifying features of the processor. More...

Data Structures
struct	features_t

Macros
#define	DR_FPSTATE_BUF_SIZE   512
#define	DR_FPSTATE_ALIGN   16
#define	FAMILY_LLANO   18
#define	FAMILY_ITANIUM_2_DC   17
#define	FAMILY_K8_MOBILE   17
#define	FAMILY_ITANIUM_2   16
#define	FAMILY_K8L   16
#define	FAMILY_K8   15
#define	FAMILY_PENTIUM_4   15
#define	FAMILY_P4   15
#define	FAMILY_ITANIUM   7
#define	FAMILY_P6   6
#define	FAMILY_IVYBRIDGE   6
#define	FAMILY_SANDYBRIDGE   6
#define	FAMILY_NEHALEM   6
#define	FAMILY_CORE_I7   6
#define	FAMILY_CORE_2   6
#define	FAMILY_CORE   6
#define	FAMILY_PENTIUM_M   6
#define	FAMILY_PENTIUM_3   6
#define	FAMILY_PENTIUM_2   6
#define	FAMILY_PENTIUM_PRO   6
#define	FAMILY_ATHLON   6
#define	FAMILY_K7   6
#define	FAMILY_P5   5
#define	FAMILY_PENTIUM   5
#define	FAMILY_K6   5
#define	FAMILY_K5   5
#define	FAMILY_486   4
#define	MODEL_HASWELL   60
#define	MODEL_IVYBRIDGE   58
#define	MODEL_I7_WESTMERE_EX   47
#define	MODEL_SANDYBRIDGE_E   45
#define	MODEL_I7_WESTMERE   44
#define	MODEL_SANDYBRIDGE   42
#define	MODEL_I7_CLARKDALE   37
#define	MODEL_I7_HAVENDALE   31
#define	MODEL_I7_CLARKSFIELD   30
#define	MODEL_ATOM_CEDARVIEW   54
#define	MODEL_ATOM_LINCROFT   38
#define	MODEL_ATOM   28
#define	MODEL_I7_GAINESTOWN   26
#define	MODEL_CORE_PENRYN   23
#define	MODEL_CORE_2   15
#define	MODEL_CORE_MEROM   15
#define	MODEL_CORE   14
#define	MODEL_PENTIUM_M   13
#define	MODEL_PENTIUM_M_1MB   9

Enumerations
enum	{   VENDOR_INTEL,   VENDOR_AMD,   VENDOR_ARM,   VENDOR_UNKNOWN }
enum	feature_bit_t {   FEATURE_FPU = 0,   FEATURE_VME = 1,   FEATURE_DE = 2,   FEATURE_PSE = 3,   FEATURE_TSC = 4,   FEATURE_MSR = 5,   FEATURE_PAE = 6,   FEATURE_MCE = 7,   FEATURE_CX8 = 8,   FEATURE_APIC = 9,   FEATURE_SEP = 11,   FEATURE_MTRR = 12,   FEATURE_PGE = 13,   FEATURE_MCA = 14,   FEATURE_CMOV = 15,   FEATURE_PAT = 16,   FEATURE_PSE_36 = 17,   FEATURE_PSN = 18,   FEATURE_CLFSH = 19,   FEATURE_DS = 21,   FEATURE_ACPI = 22,   FEATURE_MMX = 23,   FEATURE_FXSR = 24,   FEATURE_SSE = 25,   FEATURE_SSE2 = 26,   FEATURE_SS = 27,   FEATURE_HTT = 28,   FEATURE_TM = 29,   FEATURE_IA64 = 30,   FEATURE_PBE = 31,   FEATURE_SSE3 = 0 + 32,   FEATURE_PCLMULQDQ = 1 + 32,   FEATURE_DTES64 = 2 + 32,   FEATURE_MONITOR = 3 + 32,   FEATURE_DS_CPL = 4 + 32,   FEATURE_VMX = 5 + 32,   FEATURE_SMX = 6 + 32,   FEATURE_EST = 7 + 32,   FEATURE_TM2 = 8 + 32,   FEATURE_SSSE3 = 9 + 32,   FEATURE_CID = 10 + 32,   FEATURE_FMA = 12 + 32,   FEATURE_CX16 = 13 + 32,   FEATURE_xTPR = 14 + 32,   FEATURE_PDCM = 15 + 32,   FEATURE_PCID = 17 + 32,   FEATURE_DCA = 18 + 32,   FEATURE_SSE41 = 19 + 32,   FEATURE_SSE42 = 20 + 32,   FEATURE_x2APIC = 21 + 32,   FEATURE_MOVBE = 22 + 32,   FEATURE_POPCNT = 23 + 32,   FEATURE_AES = 25 + 32,   FEATURE_XSAVE = 26 + 32,   FEATURE_OSXSAVE = 27 + 32,   FEATURE_AVX = 28 + 32,   FEATURE_F16C = 29 + 32,   FEATURE_RDRAND = 30 + 32,   FEATURE_SYSCALL = 11 + 64,   FEATURE_XD_Bit = 20 + 64,   FEATURE_MMX_EXT = 22 + 64,   FEATURE_PDPE1GB = 26 + 64,   FEATURE_RDTSCP = 27 + 64,   FEATURE_EM64T = 29 + 64,   FEATURE_3DNOW_EXT = 30 + 64,   FEATURE_3DNOW = 31 + 64,   FEATURE_LAHF = 0 + 96,   FEATURE_SVM = 2 + 96,   FEATURE_LZCNT = 5 + 96,   FEATURE_SSE4A = 6 + 96,   FEATURE_PRFCHW = 8 + 96,   FEATURE_XOP = 11 + 96,   FEATURE_SKINIT = 12 + 96,   FEATURE_FMA4 = 16 + 96,   FEATURE_TBM = 21 + 96,   FEATURE_FSGSBASE = 0 + 128,   FEATURE_BMI1 = 3 + 128,   FEATURE_HLE = 4 + 128,   FEATURE_AVX2 = 5 + 128,   FEATURE_BMI2 = 8 + 128,   FEATURE_ERMSB = 9 + 128,   FEATURE_INVPCID = 10 + 128,   FEATURE_RTM = 11 + 128 }
enum	cache_size_t {   CACHE_SIZE_8_KB,   CACHE_SIZE_16_KB,   CACHE_SIZE_32_KB,   CACHE_SIZE_64_KB,   CACHE_SIZE_128_KB,   CACHE_SIZE_256_KB,   CACHE_SIZE_512_KB,   CACHE_SIZE_1_MB,   CACHE_SIZE_2_MB,   CACHE_SIZE_UNKNOWN }

Functions
size_t	proc_get_cache_line_size (void)
bool	proc_is_cache_aligned (void *addr)
ptr_uint_t	proc_bump_to_end_of_cache_line (ptr_uint_t sz)
void *	proc_get_containing_page (void *addr)
uint	proc_get_vendor (void)
int	proc_set_vendor (uint new_vendor)
uint	proc_get_family (void)
uint	proc_get_type (void)
uint	proc_get_model (void)
uint	proc_get_stepping (void)
bool	proc_has_feature (feature_bit_t feature)
features_t *	proc_get_all_feature_bits (void)
char *	proc_get_brand_string (void)
cache_size_t	proc_get_L1_icache_size (void)
cache_size_t	proc_get_L1_dcache_size (void)
cache_size_t	proc_get_L2_cache_size (void)
const char *	proc_get_cache_size_str (cache_size_t size)
size_t	proc_fpstate_save_size (void)
size_t	proc_save_fpstate (byte *buf)
void	proc_restore_fpstate (byte *buf)
bool	proc_avx_enabled (void)
void	dr_insert_save_fpstate (void *drcontext, instrlist_t *ilist, instr_t *where, opnd_t buf)
void	dr_insert_restore_fpstate (void *drcontext, instrlist_t *ilist, instr_t *where, opnd_t buf)
bool	dr_insert_get_seg_base (void *drcontext, instrlist_t *ilist, instr_t *instr, reg_id_t seg, reg_id_t reg)

Detailed Description

Utility routines for identifying features of the processor.

Macro Definition Documentation

DR_FPSTATE_ALIGN

#define DR_FPSTATE_ALIGN   16

The alignment requirements of floating point state buffer.

DR_FPSTATE_BUF_SIZE

#define DR_FPSTATE_BUF_SIZE   512

The maximum possible required size of floating point state buffer for processors with different features (i.e., the processors with the FXSR feature on x86, or the processors with the VFPv3 feature on ARM).

Note

The actual required buffer size may vary depending on the processor feature.

proc_fpstate_save_size() can be used to determine the particular size needed.

FAMILY_486

#define FAMILY_486   4

proc_get_family() processor family: 486

FAMILY_ATHLON

#define FAMILY_ATHLON   6

proc_get_family() processor family: Athlon

FAMILY_CORE

#define FAMILY_CORE   6

proc_get_family() processor family: Core

FAMILY_CORE_2

#define FAMILY_CORE_2   6

proc_get_family() processor family: Core 2

FAMILY_CORE_I7

#define FAMILY_CORE_I7   6

proc_get_family() processor family: Core i7

FAMILY_ITANIUM

#define FAMILY_ITANIUM   7

proc_get_family() processor family: Itanium

FAMILY_ITANIUM_2

#define FAMILY_ITANIUM_2   16

proc_get_family() processor family: Itanium 2

FAMILY_ITANIUM_2_DC

#define FAMILY_ITANIUM_2_DC   17

proc_get_family() processor family: Itanium 2 DC

FAMILY_IVYBRIDGE

#define FAMILY_IVYBRIDGE   6

proc_get_family() processor family: IvyBridge

FAMILY_K5

#define FAMILY_K5   5

proc_get_family() processor family: K5

FAMILY_K6

#define FAMILY_K6   5

proc_get_family() processor family: K6

FAMILY_K7

#define FAMILY_K7   6

proc_get_family() processor family: AMD K7

FAMILY_K8

#define FAMILY_K8   15

proc_get_family() processor family: AMD K8

FAMILY_K8_MOBILE

#define FAMILY_K8_MOBILE   17

proc_get_family() processor family: AMD K8 Mobile

FAMILY_K8L

#define FAMILY_K8L   16

proc_get_family() processor family: AMD K8L

FAMILY_LLANO

#define FAMILY_LLANO   18

proc_get_family() processor family: AMD Llano

FAMILY_NEHALEM

#define FAMILY_NEHALEM   6

proc_get_family() processor family: Nehalem

FAMILY_P4

#define FAMILY_P4   15

proc_get_family() processor family: P4 family

FAMILY_P5

#define FAMILY_P5   5

proc_get_family() processor family: P5 family

FAMILY_P6

#define FAMILY_P6   6

proc_get_family() processor family: P6 family

FAMILY_PENTIUM

#define FAMILY_PENTIUM   5

proc_get_family() processor family: Pentium

FAMILY_PENTIUM_2

#define FAMILY_PENTIUM_2   6

proc_get_family() processor family: Pentium 2

FAMILY_PENTIUM_3

#define FAMILY_PENTIUM_3   6

proc_get_family() processor family: Pentium 3

FAMILY_PENTIUM_4

#define FAMILY_PENTIUM_4   15

proc_get_family() processor family: Pentium 4

FAMILY_PENTIUM_M

#define FAMILY_PENTIUM_M   6

proc_get_family() processor family: Pentium M

FAMILY_PENTIUM_PRO

#define FAMILY_PENTIUM_PRO   6

proc_get_family() processor family: Pentium Pro

FAMILY_SANDYBRIDGE

#define FAMILY_SANDYBRIDGE   6

proc_get_family() processor family: SandyBridge

MODEL_ATOM

#define MODEL_ATOM   28

proc_get_model(): Atom

MODEL_ATOM_CEDARVIEW

#define MODEL_ATOM_CEDARVIEW   54

proc_get_model(): Atom Cedarview

MODEL_ATOM_LINCROFT

#define MODEL_ATOM_LINCROFT   38

proc_get_model(): Atom Lincroft

MODEL_CORE

#define MODEL_CORE   14

proc_get_model(): Core Yonah

MODEL_CORE_2

#define MODEL_CORE_2   15

proc_get_model(): Core 2 Merom/Conroe

MODEL_CORE_MEROM

#define MODEL_CORE_MEROM   15

proc_get_model(): Core 2 Merom

MODEL_CORE_PENRYN

#define MODEL_CORE_PENRYN   23

proc_get_model(): Core 2 Penryn

MODEL_HASWELL

#define MODEL_HASWELL   60

proc_get_model(): Haswell

MODEL_I7_CLARKDALE

#define MODEL_I7_CLARKDALE   37

proc_get_model(): Westmere Clarkdale/Arrandale

MODEL_I7_CLARKSFIELD

#define MODEL_I7_CLARKSFIELD   30

proc_get_model(): Core i7 Clarksfield/Lynnfield

MODEL_I7_GAINESTOWN

#define MODEL_I7_GAINESTOWN   26

proc_get_model(): Core i7 Gainestown (Nehalem)

MODEL_I7_HAVENDALE

#define MODEL_I7_HAVENDALE   31

proc_get_model(): Core i7 Havendale/Auburndale

MODEL_I7_WESTMERE

#define MODEL_I7_WESTMERE   44

proc_get_model(): Westmere

MODEL_I7_WESTMERE_EX

#define MODEL_I7_WESTMERE_EX   47

proc_get_model(): Sandybridge Westmere Ex

MODEL_IVYBRIDGE

#define MODEL_IVYBRIDGE   58

proc_get_model(): Ivybridge

MODEL_PENTIUM_M

#define MODEL_PENTIUM_M   13

proc_get_model(): Pentium M 2MB L2

MODEL_PENTIUM_M_1MB

#define MODEL_PENTIUM_M_1MB   9

proc_get_model(): Pentium M 1MB L2

MODEL_SANDYBRIDGE

#define MODEL_SANDYBRIDGE   42

proc_get_model(): Sandybridge

MODEL_SANDYBRIDGE_E

#define MODEL_SANDYBRIDGE_E   45

proc_get_model(): Sandybridge-E, -EN, -EP

Enumeration Type Documentation

anonymous enum

anonymous enum

Constants returned by proc_get_vendor().

Enumerator
VENDOR_INTEL	proc_get_vendor() processor identification: Intel
VENDOR_AMD	proc_get_vendor() processor identification: AMD
VENDOR_ARM	proc_get_vendor() processor identification: ARM
VENDOR_UNKNOWN	proc_get_vendor() processor identification: unknown

cache_size_t

enum cache_size_t

L1 and L2 cache sizes, used by proc_get_L1_icache_size(), proc_get_L1_dcache_size(), proc_get_L2_cache_size(), and proc_get_cache_size_str().

Enumerator
CACHE_SIZE_8_KB	L1 or L2 cache size of 8 KB.
CACHE_SIZE_16_KB	L1 or L2 cache size of 16 KB.
CACHE_SIZE_32_KB	L1 or L2 cache size of 32 KB.
CACHE_SIZE_64_KB	L1 or L2 cache size of 64 KB.
CACHE_SIZE_128_KB	L1 or L2 cache size of 128 KB.
CACHE_SIZE_256_KB	L1 or L2 cache size of 256 KB.
CACHE_SIZE_512_KB	L1 or L2 cache size of 512 KB.
CACHE_SIZE_1_MB	L1 or L2 cache size of 1 MB.
CACHE_SIZE_2_MB	L1 or L2 cache size of 2 MB.
CACHE_SIZE_UNKNOWN	Unknown L1 or L2 cache size.

feature_bit_t

enum feature_bit_t

Feature bits returned by cpuid. Pass one of these values to proc_has_feature() to determine whether the underlying processor has the feature.

Enumerator
FEATURE_FPU	Floating-point unit on chip
FEATURE_VME	Virtual Mode Extension
FEATURE_DE	Debugging Extension
FEATURE_PSE	Page Size Extension
FEATURE_TSC	Time-Stamp Counter
FEATURE_MSR	Model Specific Registers
FEATURE_PAE	Physical Address Extension
FEATURE_MCE	Machine Check Exception
FEATURE_CX8	OP_cmpxchg8b supported
FEATURE_APIC	On-chip APIC Hardware supported
FEATURE_SEP	Fast System Call
FEATURE_MTRR	Memory Type Range Registers
FEATURE_PGE	Page Global Enable
FEATURE_MCA	Machine Check Architecture
FEATURE_CMOV	Conditional Move Instruction
FEATURE_PAT	Page Attribute Table
FEATURE_PSE_36	36-bit Page Size Extension
FEATURE_PSN	Processor serial # present & enabled
FEATURE_CLFSH	OP_clflush supported
FEATURE_DS	Debug Store
FEATURE_ACPI	Thermal monitor & SCC supported
FEATURE_MMX	MMX technology supported
FEATURE_FXSR	Fast FP save and restore
FEATURE_SSE	SSE Extensions supported
FEATURE_SSE2	SSE2 Extensions supported
FEATURE_SS	Self-snoop
FEATURE_HTT	Hyper-threading Technology
FEATURE_TM	Thermal Monitor supported
FEATURE_IA64	IA64 Capabilities
FEATURE_PBE	Pending Break Enable
FEATURE_SSE3	SSE3 Extensions supported
FEATURE_PCLMULQDQ	OP_pclmulqdq supported
FEATURE_DTES64	64-bit debug store supported
FEATURE_MONITOR	OP_monitor/OP_mwait supported
FEATURE_DS_CPL	CPL Qualified Debug Store
FEATURE_VMX	Virtual Machine Extensions
FEATURE_SMX	Safer Mode Extensions
FEATURE_EST	Enhanced Speedstep Technology
FEATURE_TM2	Thermal Monitor 2
FEATURE_SSSE3	SSSE3 Extensions supported
FEATURE_CID	Context ID
FEATURE_FMA	FMA instructions supported
FEATURE_CX16	OP_cmpxchg16b supported
FEATURE_xTPR	Send Task Priority Messages
FEATURE_PDCM	Perfmon and Debug Capability
FEATURE_PCID	Process-context identifiers
FEATURE_DCA	Prefetch from memory-mapped devices
FEATURE_SSE41	SSE4.1 Extensions supported
FEATURE_SSE42	SSE4.2 Extensions supported
FEATURE_x2APIC	x2APIC supported
FEATURE_MOVBE	OP_movbe supported
FEATURE_POPCNT	OP_popcnt supported
FEATURE_AES	AES instructions supported
FEATURE_XSAVE	OP_xsave* supported
FEATURE_OSXSAVE	OP_xgetbv supported in user mode
FEATURE_AVX	AVX instructions supported
FEATURE_F16C	16-bit floating-point conversion supported
FEATURE_RDRAND	OP_rdrand supported
FEATURE_SYSCALL	OP_syscall/OP_sysret supported
FEATURE_XD_Bit	Execution Disable bit
FEATURE_MMX_EXT	AMD MMX Extensions
FEATURE_PDPE1GB	Gigabyte pages
FEATURE_RDTSCP	OP_rdtscp supported
FEATURE_EM64T	Extended Memory 64 Technology
FEATURE_3DNOW_EXT	AMD 3DNow! Extensions
FEATURE_3DNOW	AMD 3DNow! instructions supported
FEATURE_LAHF	OP_lahf/OP_sahf available in 64-bit mode
FEATURE_SVM	AMD Secure Virtual Machine
FEATURE_LZCNT	OP_lzcnt supported
FEATURE_SSE4A	AMD SSE4A Extensions supported
FEATURE_PRFCHW	OP_prefetchw supported
FEATURE_XOP	AMD XOP supported
FEATURE_SKINIT	AMD OP_skinit/OP_stgi supported
FEATURE_FMA4	AMD FMA4 supported
FEATURE_TBM	AMD Trailing Bit Manipulation supported
FEATURE_FSGSBASE	OP_rdfsbase, etc. supported
FEATURE_BMI1	BMI1 instructions supported
FEATURE_HLE	Hardware Lock Elision supported
FEATURE_AVX2	AVX2 instructions supported
FEATURE_BMI2	BMI2 instructions supported
FEATURE_ERMSB	Enhanced rep movsb/stosb supported
FEATURE_INVPCID	OP_invpcid supported
FEATURE_RTM	Restricted Transactional Memory supported

Function Documentation

dr_insert_get_seg_base()

bool dr_insert_get_seg_base	(	void *	drcontext,
		instrlist_t *	ilist,
		instr_t *	instr,
		reg_id_t	seg,
		reg_id_t	reg
	)

Insert code to get the segment base address pointed to by seg into register reg. In Linux, it is only supported with -mangle_app_seg option. In Windows, it only supports getting base address of the TLS segment.

Returns

whether successful.

dr_insert_restore_fpstate()

void dr_insert_restore_fpstate	(	void *	drcontext,
		instrlist_t *	ilist,
		instr_t *	where,
		opnd_t	buf
	)

Inserts into ilist prior to where meta-instruction(s) to restore the floating point state from the 16-byte-aligned buffer referred to by buf, which must be 512 bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). buf should have size of OPSZ_512; this routine will automatically adjust it to OPSZ_108 if necessary.

Note

proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

dr_insert_save_fpstate()

void dr_insert_save_fpstate	(	void *	drcontext,
		instrlist_t *	ilist,
		instr_t *	where,
		opnd_t	buf
	)

Inserts into ilist prior to where meta-instruction(s) to save the floating point state into the 16-byte-aligned buffer referred to by buf, which must be 512 bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). buf should have size of OPSZ_512; this routine will automatically adjust it to OPSZ_108 if necessary.

Note

proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

The last floating-point instruction address is left in an untranslated state (i.e., it may point into the code cache).

proc_avx_enabled()

bool proc_avx_enabled

(

void

)

Returns whether AVX is enabled by both the processor and the operating system. Even if the processor supports AVX, if the operating system does not enable AVX state saving, then AVX instructions will fault.

proc_bump_to_end_of_cache_line()

ptr_uint_t proc_bump_to_end_of_cache_line

(

ptr_uint_t

sz

)

Returns n >= sz such that n is a multiple of the cache line size.

proc_fpstate_save_size()

size_t proc_fpstate_save_size

(

void

)

Returns the size in bytes needed for a buffer for saving the floating point state.

proc_get_all_feature_bits()

features_t* proc_get_all_feature_bits

(

void

)

Returns all 4 32-bit feature values. Use proc_has_feature to test for specific features.

proc_get_brand_string()

char* proc_get_brand_string

(

void

)

Returns the processor brand string as given by the cpuid instruction.

proc_get_cache_line_size()

size_t proc_get_cache_line_size

(

void

)

Returns the cache line size in bytes of the processor.

proc_get_cache_size_str()

const char* proc_get_cache_size_str

(

cache_size_t

size

)

Converts a cache_size_t type to a string.

proc_get_containing_page()

void* proc_get_containing_page

(

void *

addr

)

Returns n <= addr such that n is a multiple of the page size.

proc_get_family()

uint proc_get_family

(

void

)

Returns the processor family as given by the cpuid instruction, adjusted by the extended family as described in the Intel documentation. The FAMILY_ constants identify important family values.

proc_get_L1_dcache_size()

cache_size_t proc_get_L1_dcache_size

(

void

)

Returns the size of the L1 data cache.

proc_get_L1_icache_size()

cache_size_t proc_get_L1_icache_size

(

void

)

Returns the size of the L1 instruction cache.

proc_get_L2_cache_size()

cache_size_t proc_get_L2_cache_size

(

void

)

Returns the size of the L2 cache.

proc_get_model()

uint proc_get_model

(

void

)

Returns the processor model as given by the cpuid instruction, adjusted by the extended model as described in the Intel documentation. The MODEL_ constants identify important model values.

proc_get_stepping()

uint proc_get_stepping

(

void

)

Returns the processor stepping ID.

proc_get_type()

uint proc_get_type

(

void

)

Returns the processor type as given by the cpuid instruction.

proc_get_vendor()

uint proc_get_vendor

(

void

)

Returns one of the VENDOR_ constants.

proc_has_feature()

bool proc_has_feature

(

feature_bit_t

feature

)

Tests if processor has selected feature.

proc_is_cache_aligned()

bool proc_is_cache_aligned

(

void *

addr

)

Returns true only if addr is cache-line-aligned.

proc_restore_fpstate()

void proc_restore_fpstate

(

byte *

buf

)

Restores the floating point state from the buffer buf. On x86, the buffer must be 16-byte-aligned, and it must be 512 (DR_FPSTATE_BUF_SIZE) bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). On ARM/AArch64, nothing needs to be restored as the SIMD/FP registers are restored together with the general-purpose registers.

Note

proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

proc_save_fpstate()

size_t proc_save_fpstate

(

byte *

buf

)

Saves the floating point state into the buffer buf.

On x86, the buffer must be 16-byte-aligned, and it must be 512 (DR_FPSTATE_BUF_SIZE) bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). On ARM/AArch64, nothing needs to be saved as the SIMD/FP registers are saved together with the general-purpose registers.

Note

proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

The last floating-point instruction address is left in an untranslated state (i.e., it may point into the code cache).

DR does NOT save the application's floating-point or MMX state on context switches! Thus if a client performs any floating-point operations in its main routines called by DR, the client must save and restore the floating-point/MMX state. If the client needs to do so inside the code cache the client should implement that itself. Returns number of bytes written.

proc_set_vendor()

int proc_set_vendor

(

uint

new_vendor

)

Sets the vendor to the given VENDOR_ constant. This function is supplied to support decoding or encoding with respect to other than the current processor being executed on. The change in vendor will be seen by the decoder and encoder, as well as the rest of the system.

Returns

the prior vendor, or -1 on an invalid argument.